Samsung Debuts Comprehensive 3D AI Memory Roadmap With zHBM, zNAND-O, And V10 BV-NAND
In Brief
Samsung unveiled next-gen AI memory at FMS 2026, showcasing zHBM, zNAND-O, and industry-first over 400 layer V10 BV-NAND for advanced AI infrastructure.
Samsung Electronics unveiled its next-generation AI memory portfolio at the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, California, presenting a comprehensive technology roadmap designed to meet the fast growing demands of high-performance computing and artificial intelligence infrastructure.
The company showcased approximately 30 memory and storage technologies at an AI cloud server-inspired booth, while Jin-Yub Lee, Executive Vice President and Head of Flash Product & Technology, and Kyungryun Kim, Vice President of the DRAM Design Team, delivered the opening keynote titled “Driving the Wave of AI Revolution: 3D Innovations in Memory & Storage Architecture.”
Vertical Architectures Redefine Memory-Processor Integration
At the center of Samsung’s vision are two concept models that fundamentally restructure how memory interfaces with processors. The company introduced zHBM, which vertically stacks high-bandwidth memory directly above AI accelerators rather than positioning it alongside the chip. Samsung states that this design minimizes data travel distance, delivering roughly eight times the performance of HBM5, more than ten times the memory density, and three times the energy efficiency, while reducing thermal resistance by over half.
The architecture also supports custom intellectual property integration between layers, enabling tailored solutions for specific accelerators. Alongside zHBM, Samsung previewed zNAND-O, a V-NAND-based solution developed in four- and eight-layer variants that combines high space efficiency with low latency for real-time edge AI workloads.
From 400-Layer NAND to Integrated Turnkey Production
Samsung also announced V10 BV-NAND, the industry’s first Bonding V-NAND architecture enabled by new wafer bonding technology. Featuring more than 400 layers, the device increases memory density by approximately 58 percent over the previous V9 generation while improving read, write, and I/O performance. The milestone arrives thirteen years after Samsung introduced the industry’s first V-NAND.
Beyond concept hardware, Samsung detailed its near-term production roadmap. Following the industry’s first mass production of HBM4 in February, the company began shipping HBM4E samples in May and exhibited its HBM5 model at FMS 2026. Samsung also showcased LPDDR5X-PIM, the industry’s first low-power DDR memory with processing-in-memory technology, which executes computations within the memory array to limit data movement and power draw.
For data center infrastructure, the PM1763 and BM1773 enterprise storage solutions were featured. As the sole integrated device manufacturer with leading capabilities across memory, foundry, and advanced packaging, Samsung highlighted its end-to-end turnkey strategy, offering integrated design and manufacturing services intended to shorten development cycles and optimize performance for AI semiconductor customers.
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Alisa, a dedicated journalist at the MPost, specializes in crypto, AI, investments, and the expansive realm of Web3. With a keen eye for emerging trends and technologies, she delivers comprehensive coverage to inform and engage readers in the ever-evolving landscape of digital finance.
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Alisa, a dedicated journalist at the MPost, specializes in crypto, AI, investments, and the expansive realm of Web3. With a keen eye for emerging trends and technologies, she delivers comprehensive coverage to inform and engage readers in the ever-evolving landscape of digital finance.
